Low latency buffer control system and method

ABSTRACT

A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffers coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention is a Continuation of Application Ser. No.10/133,908, filed Apr. 25, 2002.

FIELD OF THE INVENTION

The present invention relates to electronic circuitry and, moreparticularly, to buffer circuits for use with memories.

BACKGROUND

Memory controller circuits can be used in a variety of computer systems(e.g., desktop personal computers, notebook computers, personal digitalassistants, etc.) to facilitate the computer system's processor inaccessing memory chips. These memory chips generally include the mainmemory of the computer system, which typically includes several dynamicrandom access memory (DRAM) chips. DRAM chips include, for example,synchronous DRAM (SDRAM), extended data out (EDO) DRAM, Rambus (R)DRAM,DDR (double data rate) and DRAM chips. The memory controller typicallyincludes a memory interface for communicating with one or more of suchDRAM chips via a memory bus. The memory controller includes buffers todrive signals onto the memory bus. In addition, the memory controllertypically includes a system interface to communicate with systemprocessor(s) via a system bus. The memory controller uses theseinterfaces to route data between the processor and the DRAM chips usingappropriate address, control and data signals.

In some systems, the memory bus is terminated with resistors to amid-range voltage. As a result, if the output buffers are enabled (i.e.,pulling up or pulling down the voltage of the memory bus lines) duringidle periods, the buffers dissipate power during the idle periods. Thispower dissipation is undesirable in many applications.

One method of reducing power dissipation by the buffers during idleperiods is to implement the buffers as three-state buffers that presenta high impedance to the memory bus when disabled. Once the idle periodends, the buffers are enabled, allowing them to drive signals onto thememory bus. However, driving the voltage levels of the memory bus linestakes a finite amount of time. Thus, such systems typically have a timeperiod between when the buffers are enabled and when the signals on thememory bus are at valid logic levels. This “buffer enable” delay iflarge enough can undesirably increase latency in accessing the memory insome memory designs.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention aredescribed with reference to the following figures, wherein likereference numerals refer to like parts throughout the various viewsunless otherwise specified.

FIG. 1 is a block diagram illustrating a system with memory outputbuffer control, according to one embodiment of the present invention.

FIG. 2 is a flow diagram illustrating the operation of the systemdepicted in FIG. 1, according to one embodiment of the presentinvention.

FIG. 3 is a block diagram illustrating a portion of the memorycontroller depicted in FIG. 1, according to one embodiment of thepresent invention.

FIG. 4 is a flow diagram illustrating the operation of the memorycontroller depicted in FIG. 3, according to one embodiment of thepresent invention.

FIG. 5 is a block diagram illustrating a portion of the memorycontroller depicted in FIG. 1, according to another embodiment of thepresent invention.

FIG. 6 is a flow diagram illustrating the operation of the memorycontroller of FIG. 5, according to one embodiment of the presentinvention.

FIG. 7 is a flow diagram illustrating the operation of the memorycontroller of FIG. 5, according to another embodiment of the presentinvention.

DETAILED DESCRIPTION

FIG. 1 illustrates a system 10 having low latency buffer control,according to one embodiment of the present invention. In particular,this embodiment of system 10 includes a processor 11, a memorycontroller 12 and a memory 13. Memory 13 is a DRAM memory in theillustrated embodiment, but can be any type of memory used with a memorybus for which power dissipation is reduced when buffers driving thememory bus are disabled.

In addition, this embodiment of memory controller 12 includes a buffercontrol circuit 14 and a set of N buffers 16. FIG. 1 shows a buffer 16 ₁of the N buffers, with the remaining buffers being omitted for clarity.Buffer control circuit 14 typically includes circuitry (e.g.,combinatorial logic circuits) to provide enable signals to buffers 16,timed to reduce latency in memory accesses.

The elements of this embodiment of system 10 are interconnected asfollows. Memory controller 12 is connected to memory 13 and processor 11via system bus 18 and memory bus 17, respectively. More particularly,buffer 16 of memory controller 12 are connected to memory bus 17. Inthis embodiment, memory bus 17 has N bus lines, each being resistivelyterminated to a mid-range voltage, and system bus 18 has M bus lines.

In this embodiment of memory controller 12, buffer control circuit 14 isconnected to buffers 16. In particular, buffer control circuit 14 isconnected to the enable input terminals of buffers 16. Further, in someembodiments, buffer control circuit 14 is connected to detecttransactions being communicated on system bus 18.

FIG. 2 illustrates the operational flow of system 10 (FIG. 1) inselectively enabling buffers 16 to reduce latency, according to oneembodiment of the present invention. Referring to FIGS. 1 and 2, system10 operates as follows.

The system bus is monitored for transactions. In one embodiment, memorycontroller 12 monitors system bus 18 for transactions. Moreparticularly, buffer control circuit 14 of memory controller 12 monitorssystem bus 18 to detect transactions. This operation is represented byblocks 21 and 22.

If a transaction is detected in block 22, the operational flow proceedsto a block 24; however, if no transaction is detected in block 22, theoperational flow returns to block 21.

As shown in block 24, buffers 16 are enabled. In one embodiment, buffercontrol circuit 14 provides enable signals to the N buffers of buffers16. In this embodiment, buffers 16 are conventional three-state buffersthat present a high impedance to memory bus 17 when disabled, and eitherpull up or pull down the voltages of the bus lines of memory bus 17 whenenabled. Thus, in this embodiment, buffers 16 are enabled before thetransaction is decoded; thereby ensuring the buffers are enabled beforethey are needed to drive signals on memory bus 17. In this way, thelatency effects of the aforementioned “buffer enable” delay can besignificantly reduced or even eliminated for memory accesses.

The detected transaction is then decoded. In one embodiment, decodecircuitry in memory controller 12 decodes the transaction. One functionof the decode circuitry is to determine the “target agent” of thetransaction. For example, for memory transactions, the targeted agentwould be memory 13. Other types of transactions (e.g., PCItransactions), the targeted agent would be a different element (e.g., aPCI card). In one embodiment, the “buffer enable” delay transpiresconcurrently with the delay of the decode process, which, as describedabove, reduces or eliminates the impact of the “buffer enable” delay onmemory access latency. A block 25 represents this operation.

The decoded transaction is then evaluated to determine whether thetransaction is a memory transaction. In one embodiment, buffer controlcircuit 14 determines whether the transaction is a memory transaction bydetermining whether the decoded address is within an address rangeallocated to memory. A block 26 represents this operation.

If the transaction is a memory transaction, memory controller 12performs the memory transaction as represented by a block 27. Buffers 16are then disabled. In one embodiment, buffer controller circuit 14disables the buffers by de-asserting the aforementioned enable signals.A block 28 represents this operation.

However, if in block 26 the transaction is determined to be a non-memorytransaction (e.g., a PCI transaction), the transaction is handled by thetargeted agent as represented by a block 29. For example, memorycontroller 12 can ignore the transaction, which will also be received bythe targeted agent, thereby allowing the target agent to perform thetransaction. The operational flow then returns to block 21, with buffers16 being disabled.

FIG. 3 illustrates a portion of memory controller 12 (FIG. 1), accordingto one embodiment of the present invention. In this embodiment, memorycontroller 12 includes a transaction store 31 and a decoder 32. Inaddition, buffer control circuit 14 (FIG. 1) includes a logic circuit33.

In this embodiment, transaction store 31 stores transactions receivedfrom system bus 18. In one embodiment, transaction store 31 isimplemented with a register. Decoder 32 determines, as one of itsfunctions, the targeted agent of a received transaction. In oneembodiment, decoder 32 is substantially similar to transaction decodersused in existing memory controllers. In this embodiment, logic circuit33 includes standard logic gates to generate the enable signals providedto buffers 16 with the desired timing.

Transaction store 31 is connected to receive transactions from systembus 18. Decoder 32 is connected to the output port of transaction store31. In addition to buffers 16, logic circuit 33 is connected to anoutput port of decoder 32. Further, in this embodiment, logic circuit 33is connected to monitor transactions received by transaction store 31.As previously described, buffers 16 have output leads connected tomemory bus 17. The operation of this embodiment of memory controller 12in enabling buffers 16 is described below in conjunction with FIG. 4.

FIG. 4 illustrates the operational flow of memory controller 12 (FIG. 3)in enabling its memory interface buffers, according to one embodiment ofthe present invention. Referring to FIGS. 3 and 4, this embodiment ofmemory controller 12 operates as follows.

This embodiment of memory controller 12 operates in general as describedabove in conjunction with FIG. 2, with block 24 being described in moredetail. Although previously described, blocks 21, 22 and 24-29 aredescribed again to include the interactions with the elements of FIG. 3.

Memory controller 12 performs blocks 21 and 22 to monitor and detecttransactions being sent over the system bus. In this embodiment, logiccircuit 33 of memory controller 12 monitors system bus 18 to detecttransactions.

If logic circuit 33 does not detect a transaction in block 22, theoperational flow returns to block 21. However in this embodiment, iflogic circuit 33 does detect a transaction, logic circuit 33 assertsenable signals provided to buffers 16. The asserted enable signalsenables the buffers as described above for block 24. A block 41represents this operation.

In addition, the transaction is received by the memory controller. Inthis embodiment, transaction store 31 receives and stores thetransaction. A block 42 represents this operation. Blocks 41 and 42 ofthis embodiment are operations of block 24 (FIG. 1). Although block 42is shown in FIG. 4 as being performed after block 41, in practice block42 may be performed before or concurrently with block 41.

As previously described, because buffers 16 are enabled before thetransaction is decoded; the buffers are enabled before they are neededto drive signals on memory bus 17. Thus, the latency effects of theaforementioned “buffer enable” delay can be significantly reduced oreven eliminated for memory accesses.

Memory controller 12 then performs block 25 to decode the receivedtransaction. In this embodiment, decoder 32 of memory controller 12decodes the transaction, which includes determining the “target agent”of the transaction.

Memory controller 12 then performs block 26 to determine whether thetransaction is a memory transaction. In this embodiment, decoder 32determines the targeted agent of the transaction.

If the transaction is a memory transaction, memory controller 12performs block 27. In one embodiment, memory controller 12 performs thememory transaction using circuitry (not shown) similar to that inexisting memory controllers. Then memory controller 12 performs block 28to disable buffers 16. In this embodiment, logic circuit 33 disables thebuffers by de-asserting the aforementioned enable signals.

However, if in block 26 the transaction is not a memory transaction,memory controller 12 performs block 29, allowing the targeted agent tohandle the transaction. In one embodiment, memory controller 12 simplyignores the non-memory transaction. The operational flow then proceedsto block 21, with buffers 16 remaining disabled. Although block 28 isshown as being performed after block 29 under these circumstances, insome embodiments block 28 is performed before or concurrently with block29.

FIG. 5 illustrates a portion of memory controller 12 (FIG. 1), accordingto another embodiment of the present invention. This embodiment issimilar to the embodiment of FIG. 3, except that the transaction storeis implemented as a queue or pipeline and the buffer control circuitincludes a memory transaction detector connected to monitor transactionvia the transaction store instead of directly. More particularly, inthis embodiment, memory controller 12 includes a transaction queue 31Aand decoder 32. In addition, buffer control circuit 14 (FIG. 1) includesa logic circuit 33A and a memory transaction detector 51. In oneembodiment, memory transaction detector 51 is implemented as a decoderconfigured to decode only the address signals needed determine whetherthe transaction is a memory transaction.

In this embodiment, transaction queue 31A stores multiple transactionsreceived from system bus 18. In one embodiment, transaction queue 31A isimplemented with a FIFO (first in first out) buffer. Decoder 32 operatesas described above in conjunction with FIG. 3. Logic circuit 33A is usedin generating the enable signals provided to buffers 16, responsive tothe output signal of memory transaction detector 51.

Transaction queue 31A is connected to receive transactions from systembus 18. In addition, transaction queue 31A is connected to decoder 32and to memory transaction detector 51. Memory transaction detector 51 isconnected to logic circuit 33A, which in turn is connected to buffers16. The operation of this embodiment of memory controller 12 in enablingbuffers 16 is described below in conjunction with FIG. 6.

FIG. 6 illustrates the operation of memory controller 12 (FIG. 5) inenabling its memory interface buffers, according to one embodiment ofthe present invention. Referring to FIGS. 5 and 6, this embodiment ofmemory controller 12 operates as follows.

Memory controller 12 performs blocks 21 and 22 to monitor and detecttransactions being sent over the system bus. In this embodiment,transaction queue 31A of memory controller 12 monitors system bus 18 todetect transactions.

If transaction queue 31A does not detect a transaction in block 22, theoperational flow returns to block 21. However in this embodiment, iftransaction queue 31A does detect a transaction, transaction queue 31Areceives and stores the transaction. Transaction queue 31A can storemore than one transaction. A block 61 represents this operation.

Memory controller 12 then performs block 25 to decode a transactionstored in transaction queue 31A. More particularly, decoder 32 receivesthe “oldest” transaction stored in the transaction queue and decodes itas previously described.

Memory controller 12 then performs block 26 to determine whether thetransaction is a memory transaction. In this embodiment, decoder 32determines the targeted agent of the transaction. In the transaction isnot a memory transaction, memory controller performs block 29 (asdescribed above) and the operational flow returns to block 21.

However, if the transaction is a memory transaction, memory controller12 determines whether buffers 16 are enabled. In this embodiment, logiccircuit 33A determines whether these buffers are enabled. A block 62represents this operation.

If the buffers are not enabled, memory controller 12 performs block 41(described above) to enable the buffers. In this embodiment, logiccircuit 33A asserts the enable signals to enable buffers 16. In oneembodiment, memory controller 12 enables the buffers as previouslydescribed in conjunction with FIG. 4 by monitoring transaction queue31A.

After the buffers are enabled (either after performing block 41 or ifthe buffers were already enabled as found in block 62), memorycontroller 12 then receives the memory transaction from transactionqueue 31A, as represented by a block 63. In this embodiment, decoder 32receives the memory transaction from transaction queue 31A. Then memorycontroller 12 performs block 27 (as described previously) to execute thememory transaction.

Memory controller 12 then checks the contents of transaction queue 31Aand determines whether it contains any unexecuted memory transactions.In this embodiment, memory transaction detector 51 checks eachtransaction stored in transaction queue 31A to determine whether thetransaction is a memory transaction. In one embodiment, memorytransaction detector 51 provides a signal to logic circuit 33A thatindicates whether transaction queue 31A contains a memory transaction.Blocks 64 and 65 represent these operations. In some embodiments, memorytransaction detector 51 can be configured to check a subset of thetransactions stored in transaction queue 31A rather than all of thetransactions. For example, only the next transaction (or some smallnumber of transactions) to be performed is checked in one embodiment.This embodiment may be advantageous for relatively large transactionqueues by allowing the buffers to be disabled if the next fewtransactions in the queue are non-memory transactions.

If transaction queue 31A does not contain a memory transaction, memorycontroller 12 performs block 28 to disable buffers 16. In thisembodiment, logic circuit 33A receives the output signal from memorytransaction detector 51 and if the signal indicates that there are nopending memory transaction, logic circuit 33A de-asserts the enablesignals.

However, if transaction queue 31A does contain a memory transaction, theoperational flow returns to block 63 to receive the next transaction(which need not be a memory transaction) from transaction queue 31A,leaving buffers 16 enabled.

FIG. 7 illustrates the operation of memory controller 12 (FIG. 5),according to another embodiment of the present invention. Referring toFIGS. 5 and 7, memory controller 12 operates as follows to enablebuffers 16.

The transactions received and stored by memory controller 12 aremonitored for memory transactions. In one embodiment, memory transactiondetector 51 monitors the contents of transaction queue 31A fortransactions. A block 71 represents this operation.

The stored transactions are then checked to determine whether any arememory transactions. In one embodiment, memory transaction detector 51decodes a stored transaction to determine whether it is a memorytransaction. For example, memory transaction detector 51 may beconfigured to determine whether the transaction to be outputted bytransaction queue 31A during the next cycle is a memory transaction. Ablock 72 represents this operation.

If the transaction checked in block 72 is not a memory transaction, theoperational flow returns to block 71. However, if the transaction is amemory transaction, block 41 is performed as described above to enablethe buffers. In this embodiment, memory transaction detector 51 providesa signal to logic circuit 33A to assert the enable signals provided tobuffers 16.

Memory controller 12 then performs block 25 to decode a transactionstored in transaction queue 31A. More particularly, decoder 32 receivesthe “oldest” transaction stored in the transaction queue and decodes itas previously described.

Memory controller 12 then performs block 26 to determine whether thistransaction is a memory transaction. In this embodiment, decoder 32determines this targeted agent of the transaction to determine whetherthe transaction is a memory transaction.

If this transaction is a memory transaction, memory controller 12performs block 27 as previously described to execute the memorytransaction and then block 28 to disable buffers 16. In this embodiment,logic circuit 33A de-asserts the enable signals to disable buffers 16.However, if the transaction is not a memory transaction, memorycontroller 12 performs block 29 as previously described, allowing thetargeted agent to perform the transaction.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

In addition, embodiments of the present description may be implementednot only within a semiconductor chip but also within machine-readablemedia. For example, the designs described above may be stored uponand/or embedded within machine readable media associated with a designtool used for designing semiconductor devices. Examples include anetlist formatted in the VHSIC Hardware Description Language (VHDL)language, Verilog language or SPICE language. Some netlist examplesinclude: a behavioral level netlist, a register transfer level (RTL)netlist, a gate level netlist and a transistor level netlist.Machine-readable media also include media having layout information suchas a GDS-II file. Furthermore, netlist files or other machine-readablemedia for semiconductor chip design may be used in a simulationenvironment to perform the methods of the teachings described above.

Thus, embodiments of this invention may be used as or to support asoftware program executed upon some form of processing core (such as theCPU of a computer) or otherwise implemented or realized upon or within amachine-readable medium. A machine-readable medium includes anymechanism for storing or transmitting information in a form readable bya machine (e.g., a computer). For example, a machine-readable medium caninclude such as a read only memory (ROM); a random access memory (RAM);a magnetic disk storage media; an optical storage media; and a flashmemory device, etc. In addition, a machine-readable medium can includepropagated signals such as electrical, optical, acoustical or other formof propagated signals (e.g., carrier waves, infrared signals, digitalsignals, etc.).

Although the present invention has been described in connection with apreferred form of practicing it and modifications thereto, those ofordinary skill in the art will understand that many other modificationscan be made to the invention within the scope of the claims that follow.Accordingly, it is not intended that the scope of the invention in anyway be limited by the above description, but instead be determinedentirely by reference to the claims that follow.

1. A method, comprising: monitoring a first bus for transactions;enabling at least one buffer when a transaction is detected, the atleast one buffer to drive a signal on a second bus; determining whetherthe detected transaction is a memory transaction; and disabling the atleast one buffer if the transaction is not a memory transaction.
 2. Themethod of claim 1, further comprising decoding the detected transaction.3. The method of claim 1, further comprising storing the detectedtransaction in a storage element.
 4. The method of claim 1, terminatingthe second bus to a mid-range voltage.
 5. An apparatus, comprising:means for monitoring a first bus for transactions; a buffer to drive asignal on a targeted memory bus; means for enabling the buffer when atransaction is detected; means for determining whether the detectedtransaction is a transaction for a device coupled to the targeted memorybus; and means for disabling the buffer if the detected transaction isdetermined not to be a transaction for a device coupled to the targetedmemory bus.
 6. The apparatus of claim 5, further comprising means forreceiving the transaction.
 7. The apparatus of claim 6, wherein themeans for receiving includes a storage device.
 8. The apparatus of claim5, wherein the second bus is terminated to a mid-range voltage.
 9. Amethod, comprising: monitoring a transaction queue; decoding atransaction in the transaction queue; determining whether the decodedtransaction is a memory transaction; and disabling at least one buffercoupled to a memory bus if the transaction is not a memory transaction.10. The method of claim 9, further comprising presenting a highimpedance to the memory bus when the buffer is disabled.
 11. The methodof claim 9, further comprising terminating the memory bus to a mid-rangevoltage.
 12. A method, comprising: monitoring a first bus to detecttransactions; storing detected transactions in a queue; decoding atransaction being output by the queue; determining whether the decodedtransaction is targeted for a memory bus; enabling at least one bufferif not already enabled if the decoded transaction is targeted for thememory bus, the at least one buffer being coupled to the memory bus; anddisabling the at least one buffer if the decoded transaction is nottargeted for the memory bus.
 13. The method of claim 12, furthercomprising delaying performance of the decoded transaction until afterenabling the at least one buffer.
 14. The method of claim 13, furthercomprising: performing the decoded transaction; and disabling the atleast one buffer after performing the decoded transaction.
 15. A method,comprising: monitoring a first bus to detect transactions; storingdetected transactions in a queue; decoding a transaction being output bythe queue; determining whether the transaction is a memory transaction;determining whether a plurality of buffers are enabled, wherein theplurality of buffers are coupled to a second bus; enabling the pluralityof buffers if the transaction is a memory transaction; determiningwhether the transactions stored in queue are memory transactions; anddisabling the plurality of buffers if the transaction is not a memorytransaction.
 16. The method of claim 15, further comprising disablingthe plurality of buffers after performing the memory transaction. 17.The method of claim 16, further comprising the plurality of bufferspresenting a high impedance to the memory bus.
 18. The method of claim17, further comprising terminating the memory bus to a mid-rangevoltage.
 19. The method of claim 16, further comprising decoding thememory transaction.
 20. The method of claim 19, further comprisingenabling the plurality of buffers while the memory transaction is beingdecoded.
 21. A system comprising: a processor; a synchronous dynamicrandom access memory (SDRAM); a memory controller coupled to theprocessor and to the SDRAM, wherein the memory controller includes: aplurality of buffers coupled to a terminated memory bus; a decoder todecode a transaction sent by the processor; and a buffer controlcircuit, coupled to the decoder and the plurality of buffers, to detectthe transaction and, in response thereto, to enable the plurality ofbuffers before the decoder completes decoding the transaction, whereinthe buffer control circuit is configurable to determine whether thetransaction is a memory transaction and to disable the plurality ofbuffers if the transaction is not a memory transaction.
 22. The systemof claim 21, wherein the memory controller further comprises atransaction store coupled to the decoder.
 23. The system of claim 22,wherein the transaction store comprises a queue.
 24. A systemcomprising: a processor; a synchronous dynamic random access memory(SDRAM); a memory controller coupled to the processor and the SDRAM,wherein the memory controller includes: a plurality of buffers coupledto a memory bus, the memory bus being terminated to a mid-range voltage;a transaction store to store transactions sent by the processor; adecoder coupled to the transaction store to decode a transaction beingoutput by the transaction store; and a buffer control circuit coupled tothe transaction store and the plurality of buffers, wherein the buffercontrol circuit is configurable to disable the plurality of buffersafter the transaction is performed if the transaction store does notcontain other transactions targeted for the terminated memory bus,wherein the buffer control circuit is further configurable to determinewhether a decoded transaction from the transaction store is targeted forthe memory bus and in response thereto enable the plurality of buffersif they are not already enabled.
 25. The system of claim 24, wherein thebuffer control circuit is further configurable to allow the plurality ofbuffers to remain enabled after the transaction is performed if thetransaction store does contain a transaction targeted for the memorybus.
 26. The system of claim 24, wherein the transaction store comprisesa queue.
 27. The system of claim 24, wherein the buffer control circuitis further configurable to delay performance of the decoded transactionafter enabling the plurality of buffers.